IEC 61523-2:2002 pdf download

IEC 61523-2:2002 pdf download.Delay and power calculation standards -Part 2: Pre-layout delay calculation specificationfor cMos ASIC libraries.
The delay calculation method addressed in this standard consists of
1) Estimation of wire capacitance and
2) Delay calculation method based on tablelook-up.
With use of DCL and SDF, this delay calculation method helps the user have a
unified timing model for various EDA tools in the pre-layout design phase.
This standard is consistent with existing standards and accepts existing standard formats, like SPEF, DCL, and SDF.
Scope of this standard covers the CMOS ASIC front end timing design for using logic synthesizer, simulators, timing verifiers. The delay calculation method specified is based on the input slew rate calculation step and the port to port calculation step.
During these calculation steps, the table lookup method is used. The table method of this standard specifies two interpolation methods for delay calculation. One is bi-linear interpolation which is widely used through the industry. Another is a linear interpolation using neighboring 3 points.
The nature of the delay value has monotonously increasing function of convex surface. This linear interpolation has a few percent of differences between linear interpolation and SPICE result.
2. Normative references
The following referenced documents arc indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies
IEEE Standard 1481:1999, Integrated circuit (IQ Delay and Power calculation System.
3. Relations with other companion standards activities
The input to the delay calculator are net list and library.
The net list is described on either Verilog or VHDL.
The library consists of a functional part and a delay parameter part.
The functional part of the library is covered by Verilog or VHDL.
NOTE The delay parameter part of the library has not been standardized, because it depends strongly on the delay calculation method. EIAJ/ALR version 1.1 described the delay calculation method , and the delay calculation method of EIAJ/ALR versionl.1 is represented by DCL and DCL-P1 standard(IEEE 1481).
This part of IEC 61523 specifies in detail a table look up calculation formula for CMOS ASIC library’.
The output of the delay calculator is a Standard Delay Format (SDF).
4. Terms and Definitions
capacitance of the net: Net means equipotential signal pins which will be connected by routing. The capacitance of the net is the capacitance of all the signal pins tha tare connected by routing.
CMOS: Complementary Metal Oxide Semiconductor.
DCL: Delay Calculation Language.
front end design: Logical design phase of ASIC design. Back end design means layout design.
gate: module containing only one output which is a simple boolean function of its inputs. Some basic simple boolean functions are and/or/not.
input slew rate: Slope of the input signal of the gate.In CMOS,the gate output delay is the function of its input slope of the signal.
load capacitance: Capacitance driven by gate. Usually it is separated into two items: i.e. wiring load capacitance and the sum of input load capacitance.
logic synthesizer: CAD package function performing the translation from RTL-level descriptions to Gate-level descriptions.
port to port delay: One meaning is pin to pin delay inside of gate. The other is pin to pin delay between gates.
pre-layout: Design phase before layout, i.e.logical design phase. propagation delay: Traveling time of a given edge of a signal. Usually it is
separated into two items: i.e.propagation delay inside a gate and propagation
delay from the output of a gate to the input of another gate which is driven by it.
SDF: Standard Delay Format.
simulator: CAD package function of the circuit simulator based on behavior, network, and stimulus. There are Digital and Analog Simulators.
SPEF: Standard Parasitic Exchangeable Format.
SPICE: Simulation Program similar to the program with the same name developed at UC Berkeley. The simulation results are in terms of continuous waveforms representing current or voltage. It emphasizes Integrated Circuit timing and waveforms.