IEEE 1149.10-2017 pdf download
IEEE 1149.10-2017 pdf download.IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture.
i. The scan-channel interface shall assert Reset 10* for a period of time determined by the designer and then de-assert it.
and
ii. The dc-assert shall occur prior to any capture, shift, or update event which occurs due to the receipt of a SCAN packet.
NOTE—The length of time here cannot be unreasonable. It is possible thr the transmitter to send a RESET packet immediately followed by a SCAN packet without IDLE states in between.
g) When a RESET packet is received and the TYPE field bit position TRSTIO is a logic one, and the optional TRST1O* output is provided [see permission 5.1.2 y)], the scan-channel interface shall assert the signal TRST1O*.
h) When a RESET packet is received and the TYPE field hit position TRST1O is a logic zero, the scan-channel interface shall dc-assert TRST 10*.
NOTE—Asserting the signal Reset 10* or the signal TRST1O* does not change HSTAP compliance. See rule 4.1.2 e). This implies that scan registers documented in the P[)L iProc Disable_1149_1O must be initialized to mission mode operation using POR or other initialization method.
i) The PEDDA shall include a 16-bit TARGET_ID register.
j) The PEDDA shall be designed such that at power-on-reset or when IEEE 1149.10 compliance is enabled, the PEDDA’s TARGET_ID register contents shall be set to all zeros.
k) The PEDDA shall be designed such that when the PEDDA’S TARGET_ID is all zeros, all packets received except the CONFIG packet are forwarded for transmission.
I) The PEDDA shall be designed such that a received CONFIG packet shall change the TARGET_ID register to the value specified by the
m) The TARGET_ID register shall retain its contents unless one of the following occurs:
i. The PEDDA circuit is powered-off.
ii. A RESET packet is received with the TYPE field TARGET_ID bit is a logic one.
iii. IEEE 1149.10 compliance is disabled via the TAP.
n) When a RESET packet is received and the TYPE field bit position TARGET_ID is a logic one, the scan-channel interface shall set the TARGET_ID register to all zeros.
o) The PEDDA shall be designed such that a received TARGET packet that has a TARGET_ID that matches the TARGET_ID of the PEDDA, all subsequent packets received until the next TARGET packet received shall be operated on by the PEDDA.
p) The PEDDA shall be designed such that when a TARGET packet is received that has a TARGET_ID that does not match the TARGET_ID of the PEDDA, all subsequent packets until the next TARGET packet received shall be forwarded for transmission.
q) The PEDDA shall be dcsigncd such that a received CONFIG packet with an incorrect CRC32 shall have no effect on the TARGET_ID register.
r) The PEDDA shall be designed such that a received TARGET packet with an mcorrect CRC’32 shall have no effect on the operation of the PEDDA other than to return an ERROR_CHAR.
s) The PEDDA shall be designed such that a received RAW packet with an incorrect CRC32 shall have no effect on the operation of the PEDDA other than to return an ERROR_CHAR.
t) The PEDDA shall be designed such that if it has access to an IEEE 1149.1 boundary-scan register, said boundary-scan register shall have boundary-scan cells associated with the HSTAP signals on an excludable segment.
NOTE—If IEEE 1149.10 is used to take a device into EXTEST, EXTEST PULSE, EXTEST_TRAIN,
SELECTIVE TOGGLE, the boundary-scan register needs to be segmented at the HSTAP such that the
1-ISTAP signals remain in mission-mode. See IEEE Std 1149.1 for details on excludable segments. See Figure 9.
